The present invention relates to a semiconductor integrated circuit device provided with level shift circuits for shifting the potential level of a signal input or output into/from an internal logic circuit from/to the outside.
With the recent process scaling-down achievement, the power supply voltage for internal circuits of a semiconductor integrated circuit tends to be increasingly lowered. In systems such as electronic equipment, however, some semiconductor elements used in the systems still adopt the conventional power supply voltage. Therefore, in such a system, on the occasion of conducting transmission/reception of a signal between such a semiconductor element and a semiconductor integrated circuit, a level shift circuit for shifting the voltage level of the signal is generally provided inside the semiconductor integrated circuit, to thereby secure interface between the semiconductor element and the semiconductor integrated circuit different in power supply voltage.
Also, recently, a power supply voltage optimum for each circuit block is supplied individually inside a semiconductor integrated circuit to attain power reduction. In this case, also, a level shift circuit is used for securing interface between circuit blocks different in power supply voltage.
Under the circumstances described above, in a semiconductor integrated circuit provided with level shift circuits, the level shift circuits are placed inside I/O cells as the interface section located around the periphery of an internal logic circuit, to perform a voltage level shift between the internal voltage of the semiconductor chip and the external voltage, as described in Japanese Patent Gazette No. 3233627, for example.
FIG. 1 shows a schematic layout of such a semiconductor integrated circuit (semiconductor chip). Referring to FIG. 1, the reference numeral 100 denotes a semiconductor substrate, 102 an internal logic circuit region, and 101 an I/O region located around the periphery of the internal logic circuit region 102. In the I/O region 101, a plurality of I/O cells (in the illustrated example, only three I/O cells 21, 22 and 23 are shown) are placed in line. Corner cells 103 are placed in the corners of the semiconductor substrate 100.
FIG. 2 shows an exemplified internal configuration of one of the I/O cells (I/O cell 21, for example). The illustrated I/O cell 21, which is for input/output of a signal (input/output cell 21), is largely divided into four sections: a pad 1 for external connection, a function section 18, a control section 19 and a level shift section 20. The function section 18 includes an input circuit 2, an output circuit 3, a pull-up/pull-down circuit 4 and an ESD protection circuit 5. The input circuit 2 has an input function of inputting a signal sent from outside the semiconductor chip into the internal logic circuit 16 in the semiconductor chip. The output circuit 3 has an output function of outputting a signal from the internal logic circuit 16 to outside the semiconductor chip. The pull-up/pull-down circuit 4 has a pull-up/pull-down function for fixing the pad 1 at “H” or “L” level when the input/output cell 21 is in neither the signal input state nor the signal output state. The ESD protection circuit 5 has a function of protecting circuits in the semiconductor chip from electrostatic discharge (ESD).
The control section 19 includes: an input control circuit 6 and an output control circuit 7 for controlling the input circuit 2 and the output circuit 3, respectively, as well as making sure that the signal input function and the signal output function never occur simultaneously; an output current switch control circuit 8 for switching the output current capability of the output circuit 3 among a plurality of stages; a pull-up/pull-down ON/OFF control circuit 9 for controlling operation/non-operation of the pull-up/pull-down circuit 4; and a pull-up/pull-down switch control circuit 10 for controlling which function of the pull-up/pull-down circuit 4, the pull-up function or the pull-down function, is to be used. The control circuits 6 to 10 of the function section 19 are respectively constructed of transistors operating with an external voltage.
The level shift section 20 includes a level shift circuit 11 for the input circuit 2 and six level shift circuits 12a to 12c and 13a to 13c for the control circuits 6 to 10 of the control section 19. When the internal logic circuit 16 is a circuit operating with low-voltage power supply, each of these level shift circuits will be a level shift-up circuit if configured to receive a signal from the internal logic circuit 16 or a level shift-down circuit if configured to output a signal to the internal logic circuit 16.
In the conventional semiconductor integrated circuit described above, a total of seven level shift circuits are necessary for the I/O cell 21 having the input/output function (input/output cell 21) shown in FIG. 2, for example, and this increases the size of the I/O cell. With the recent implementation of system LSI, the necessary number of pins for a semiconductor chip increases. Under this circumstance, with the increase in the size of one I/O cell, the I/O region including I/O cells of the number equal to the necessary number of pins will also become large. As a result, the size of the semiconductor chip will be determined with the size of the I/O region, and this will cause disadvantages such as having wasteful space unused for placement of circuits in the internal logic circuit placement region.
As a solution for the above, it may be suggested that a plurality of level shift circuits may be placed in the logic circuit placement region inside the semiconductor chip, for example. However, this will also lead to increase in the area of the semiconductor chip, and thus should not be adopted.